Designing DRO (Dielectric Resonant Oscillators ) and PLOs (Phase Lock Oscillators)

RADITEK offers free running Dielectric Resonant Oscillators (DRO) as well as Phase Locked (PLO or PLDRO) and synthesized oscillators (RSPLO).

In the PLO circuit design stage, we often need to characterize the designed PLL response in the linear operating region as well as the non-liner operating region.

The Phase Locked loop (PLL) works in the linear operating region when it is locked to a reference frequency usually less than 1GHz. The most comprehensive test method to measure the PLL response/phase noise, in the PLL linear operating region is the phase noise measurement on a low phase noise/spurious spectrum analyzer, with high dynamic range.

There are also the non-linear operating characteristics to be considered. A PLL needs to change its output frequency and during the fast signal transition, the PLL goes temporarily non-linear. Such RF transientsshort term characteristics are known as lockup time. Most digital communication systems require fast frequency switching because of any available time slot for carrier acquisition gets smaller. The requirement of lock up time is about 10microseconds and below. So we need faster sampling rates to maintain sufficient frequency or phase resolution. A frequency synthesizer may need to cover increase bandwidth, in a given communication system.

RADITEK can design to any custom requirement, of extreme environment and frequency/phase noise requirement. Plus fast switching and other special requirements if needed.